About MEET2024

Welcome to MEET2024! Join us for an unforgettable experience filled with excitement, inspiration, and connection. Our event brings together industry leaders, experts, and enthusiasts to share knowledge, engage in meaningful discussions, and foster valuable connections. Explore innovative ideas, discover new opportunities, and be a part of this vibrant gathering. Whether you’re a seasoned professional or a curious newcomer, there’s something for everyone at MEET2024. Get ready for a day of learning, networking, and fun. See you there!

Agenda

(All times are in SGT)

Agenda

November 12, 2024 01:30 pm

Conference Opening and Marvell CTO Strategy

Noam Mizrahi

November 12, 2024 02:00 pm

Marvell Product Strategy

Raghib Hussain

November 12, 2024 02:30 pm

Accelerated Infra - Connectivity

Achyut Shah

November 12, 2024 03:00 pm

Technology and Development

Sandeep Bharathi

November 12, 2024 03:30 pm

External Keynote: Space Exploration: Strategy of Innovation and Risk Management

Dr. Lindy Elkins-Tanton

November 12, 2024 04:00 pm

Break

November 12, 2024 04:10 pm

Switch for Data Center

Puneet Agarwal

November 12, 2024 04:30 pm

Custom ASICs

Mark Kuemerle

November 12, 2024 04:50 pm

Enterprise and Carrier

Tejas Bhatt

November 12, 2024 05:10 pm

Break

November 12, 2024 05:20 pm

Automotive

Amir Bar-Niv

November 12, 2024 05:50 pm

Operations

Ramanan Thiagarajah

November 12, 2024 06:00 pm

AI for Marvell

Jon Haswell

November 12, 2024 06:25 pm

Wrap Up - Day 2 and Day 3 Sneak Peak

Bill Reaves

November 13, 2024 01:20 pm

Track 1: Digital Design or DF(X)

Explore the latest in digital design and DF(x) methodologies, including high-level synthesis, low-power techniques, advanced scan testing over PCIe, automated DFT diagnostics using large language models, and innovative chiplet communication solutions. Gain insights from real-world case studies and practical implementations that enhance performance, efficiency, and reliability, leading to first-time-right silicon, reduced development cycles, and improved product quality.

November 13, 2024 01:30 pm

High Level Synthesis, An Introduction with Tool Evaluation Results and Lessons Learned

Alfredo Taddei

November 13, 2024 01:50 pm

Q&A: High Level Synthesis, An Introduction with Tool Evaluation Results and Lessons Learned

Q&A

November 13, 2024 02:00 pm

Algorithmically Generating Maximally Stride Resistant Linear Hashes in Deterministic Time

Robert Murphy

November 13, 2024 02:20 pm

Q&A: Algorithmically Generating Maximally Stride Resistant Linear Hashes in Deterministic Time

Q&A

November 13, 2024 02:30 pm

Packet Delay Variation Reduction Techniques in MultiGig Ethernet Design

Jeff Zheng

November 13, 2024 02:50 pm

Q&A: Packet Delay Variation Reduction Techniques in MultiGig Ethernet Design

Q&A

November 13, 2024 03:00 pm

Efficient Low Power Design through Early Power Analysis and SEC

Neenu Prince Kiluthattil

Mira Kim

November 13, 2024 03:20 pm

Q&A: Efficient Low Power Design through Early Power Analysis and SEC

Q&A

November 13, 2024 03:30 pm

Bridging the Chiplet Gap

Michael Vandegriend

November 13, 2024 03:50 pm

Q&A: Bridging the Chiplet Gap

Q&A

November 13, 2024 04:00 pm

Tessent SSN Shift & Capture Clock Timing Controls

Tange Barbour

November 13, 2024 04:20 pm

Q&A: Tessent SSN Shift & Capture Clock Timing Controls

Q&A

November 13, 2024 04:30 pm

Scan Over PCIe: New Era in ATPG Testing Through Entire Si Life Cycle

Vlad Goldman

November 13, 2024 04:50 pm

Q&A: Scan Over PCIe: New Era in ATPG Testing Through Entire Si Life Cycle

Q&A 

November 13, 2024 05:00 pm

Navigating with Co-Pilot: A Case Study in DFT Diagnostics Automation Using LLMs

Ravi Murthy

November 13, 2024 05:20 pm

Q&A: Navigating with Co-Pilot: A Case Study in DFT Diagnostics Automation Using LLMs

Q&A

November 13, 2024 01:20 pm

Track 2: Analog Design, Optical / Physical Layer Design

This track covers analog and optical technologies, from chiplets and smart die-to-die interconnects to high-performance, long-reach and optical links. Discover serial link transmitters, receivers, and Silicon Photonics. Learn about Marvell’s future investments in high bandwidth analog, optics, and storage pre-amp technologies. 

November 13, 2024 01:30 pm

Chiplet Technologies and Marvell's IP Solutions to Enable Hetrogenous Integration

Mark Kuemerle

November 13, 2024 01:50 pm

Q&A: Chiplet Technologies and Marvell's IP Solutions to Enable Hetrogenous Integration

Q&A

November 13, 2024 02:00 pm

Industry’s Longest Reach 224Gbps Receiver with Best-In-Class Performance and Efficiency

Manisha Gambhir

Davide Visani

November 13, 2024 02:20 pm

Q&A: Industry’s Longest Reach 224Gbps Receiver with Best-In-Class Performance and Efficiency

Q&A

November 13, 2024 02:30 pm

224Gbps Integrated Sipho/EML Driver for AI Cluster Optical Interconnect

Li Cai

Vivek Gurumoorthy

November 13, 2024 02:50 pm

Q&A: 224Gbps Integrated Sipho/EML Driver for AI Cluster Optical Interconnect

Q&A

November 13, 2024 03:00 pm

A 0.86pJ/b 224Gb/s DAC-based Transmitter in 5nmFinFET

Peng (MSI) Liu

November 13, 2024 03:20 pm

Q&A: A 0.86pJ/b 224Gb/s DAC-based Transmitter in 5nmFinFET

Q&A

November 13, 2024 03:30 pm

Next Generation Coherent 120GHz Analog Front-End

Tzu-Fan Wu

November 13, 2024 03:50 pm

Q&A: Next Generation Coherent 120GHz Analog Front-End

November 13, 2024 04:00 pm

Industry's Widest Bandwidth Amplifier Technology: Today and Tomorrow

Carl Pobanz

November 13, 2024 04:20 pm

Q&A: Industry's Widest Bandwidth Amplifier Technology: Today and Tomorrow

Q&A

November 13, 2024 04:30 pm

Microring-based Si photonics

Charles Lin

November 13, 2024 04:50 pm

Q&A: Microring-based Si photonics

Q&A

November 13, 2024 05:00 pm

Optical I/O for Silicon Photonics

Jun Rong Ong

November 13, 2024 05:20 pm

Q&A: Optical I/O for Silicon Photonics

Q&A

November 13, 2024 01:20 pm

Track 3 : Design Verification or Validation

This track features posters and presentations on the latest advancements for ensuring the reliability and performance of complex IP and SoCs (System-on-a-Chips). Explore cutting-edge methodologies, tools, and technologies that drive the design verification, emulation, and validation processes. Examine the benefits of co-emulation, validation techniques for product security testing, best practices of formal verification, and the use of generative AI to create assertions. 

November 13, 2024 01:30 pm

Innovative Approach for Optical Bandwidth Validation In Transimpedance Amplifiers

Yan Linn

November 13, 2024 01:50 pm

Q&A: Innovative Approach for Optical Bandwidth Validation In Transimpedance Amplifiers

Q&A

November 13, 2024 02:00 pm

Automated Functional Coverage Driven Tests Generation for Faster Verification Closure

Karthik Mohan

November 13, 2024 02:20 pm

Q&A: Automated Functional Coverage Driven Tests Generation for Faster Verification Closure

Q&A
November 13, 2024 02:30 pm

Using Generative AI to Create SystemVerilog Assertions

Jonathan Ebbers

Barb Powers

November 13, 2024 02:50 pm

Q&A: Using Generative AI to Create SystemVerilog Assertions

Q&A
November 13, 2024 03:00 pm

Synthesizable Channel Model for Coherent Lite Application

John Lin

November 13, 2024 03:20 pm

Q&A: Synthesizable Channel Model for Coherent Lite Application

Q&A
November 13, 2024 03:30 pm

4ns Skew Injection Test in Nova Die-to-Die 1.6T ODSP

Zhupei Shi

November 13, 2024 03:50 pm

Q&A: 4ns Skew Injection Test in Nova Die-to-Die 1.6T ODSP

Q&A
November 13, 2024 04:00 pm

Transaction Tracking Using Global Unique Identifiers

Catherine Choi

November 13, 2024 04:20 pm

Q&A: Transaction Tracking Using Global Unique Identifiers

Q&A
November 13, 2024 04:30 pm

A Formal Verification Methodology for Clock-Gating

Shahid Ikram

Gabriel Bischoff

Dan Dever

November 13, 2024 04:50 pm

Q&A: A Formal Verification Methodology for Clock-Gating

Q&A
November 13, 2024 05:00 pm

DRANDs, Runtime Constrained Random Variables for Greater Control and Efficiency of Testing

Michael Rivera

November 13, 2024 05:20 pm

Q&A: DRANDs, Runtime Constrained Random Variables for Greater Control and Efficiency of Testing

Q&A
November 13, 2024 01:20 pm

Track 4: Architecture or Algorithms

This track delves into critical innovations driving our industry forward. Explore how cutting-edge advancements in chip architecture and algorithm optimization ensure our products not only meet but exceed market demands. 

Join us to uncover the breakthroughs that will shape the future of technology and secure our position at the forefront of innovation.

November 13, 2024 01:30 pm

Ultra Ethernet Innovations for AI Networks

Brad Matthews

November 13, 2024 01:50 pm

Q&A: Ultra Ethernet Innovations for AI Networks

Q&A
November 13, 2024 02:00 pm

PCIe Gen 6 and beyond: Evolution, Features, Implementation, Performance

Yuanjie Chen

Andrew Huang

November 13, 2024 02:20 pm

Q&A: PCIe Gen 6 and beyond: Evolution, Features, Implementation, Performance

Q&A
November 13, 2024 02:30 pm

The Accelerating Trend of Custom HBM

Sid Allman

November 13, 2024 02:50 pm

Q&A: The Accelerating Trend of Custom HBM

Q&A
November 13, 2024 03:00 pm

Optimizing AI Inference at the Edge Through OneMarvell Technology

Jack Harwood

November 13, 2024 03:20 pm

Q&A: Optimizing AI Inference at the Edge Through OneMarvell Technology

Q&A
November 13, 2024 03:30 pm

Asymmetric Modulation – From Marvell’s Innovation Contest to a Test Chip and Standardization

Alireza Razavi

Ragnar Jonsson

November 13, 2024 03:50 pm

Q&A: Asymmetric Modulation – From Marvell’s Innovation Contest to a Test Chip and Standardization

Q&A
November 13, 2024 04:00 pm

System Modeling of Next Generation Coherent Optical Modules

Stewart Clelland

November 13, 2024 04:20 pm

Q&A: System Modeling of Next Generation Coherent Optical Modules

Q&A
November 13, 2024 04:30 pm

Power-Efficient Multi-Stage Processing Algorithms Applied to Forward Error Correction Decoding

Genaro Bergero

November 13, 2024 04:50 pm

Q&A: Power-Efficient Multi-Stage Processing Algorithms Applied to Forward Error Correction Decoding

Q&A
November 13, 2024 05:00 pm

Confidential Key Store

Phanikumar Kancharla

November 13, 2024 05:20 pm

Q&A: Confidential Key Store

Q&A
November 13, 2024 01:20 pm

Track 9: Marvell Fundamental Technology/Product Overview

These presentations will provide everyone at Marvell with a clear and concise understanding of the technologies and strategic initiatives driving our success. This is a great opportunity to grasp the end-to-end lifecycle of a Marvell product. 

On Day 2, experience the entire process of designing a computer chip (SoC – System on Chip), from inception through fabrication to production. Dive into the role of an architect, logic designer, analog layout engineer, package designer, physical designer, and many more roles at Marvell. Virtually visit some of our labs and test facilities to see the products in action. 

November 13, 2024 01:30 pm

Lifecycle of a Marvell Chip Overview

Jeanne Trinko Mechler

November 13, 2024 01:50 pm

Q&A: Lifecycle of a Marvell Chip Overview

Q&A

November 13, 2024 02:00 pm

Product Architecture and System Modeling

Shahe Krakirian

Rupa Budhia

Eric Hung

November 13, 2024 02:20 pm

Q&A: Product Architecture and System Modeling

Q&A

November 13, 2024 02:30 pm

Analog and Foundational IP Design

Priyanka Sharma

Darren Anand

Vathsala Sollepura Manjegowda

Jie Lin

November 13, 2024 02:50 pm

Q&A: Analog and Foundational IP Design

Q&A

November 13, 2024 03:00 pm

Logic Design, Design-For-Test, and Pre-Silicon Verification

Nagaraj Shirali

Nick Jamba

Kevin Gorman

November 13, 2024 03:20 pm

Q&A: Logic Design, Design-For-Test, and Pre-Silicon Verification

Q&A

November 13, 2024 03:30 pm

Physical Design and Package Design

Karthik Anand Ambigapathi

Vidya Panduranga Rao

Greg Ford

Ellie Baghernia

November 13, 2024 03:50 pm

Q&A: Physical Design and Package Design

Q&A

November 13, 2024 04:00 pm

Fabrication, Assembly, and Test

Runzi Chang

Jason DiRosa

November 13, 2024 04:20 pm

Q&A: Fabrication, Assembly, and Test

Q&A

November 13, 2024 04:30 pm

Software and Hardware Validation

Deepak Govind Choudhary

November 13, 2024 04:50 pm

Q&A: Software and Hardware Validation

Q&A

November 13, 2024 05:00 pm

High Volume Production

Jeanne Trinko Mechler

Bimla Paul

Greg Bazan

November 13, 2024 05:20 pm

Q&A: High Volume Production

Q&A

November 14, 2024 01:20 pm

Track 5: Back End or Physical Design

Physical Design experts will showcase the latest advancements in design implementation methodologies.

Learn about a variety of essential topics for robust and efficient IC design such as innovative approaches to clock mesh and feedthrough implementation, advanced proven techniques for minimizing IR drop, power integrity enhancements, and improvements in the accuracy of EMIR signoff through precise modeling. Additionally, understand methodologies like Tempus-PI, SMVA-based timing corner optimization, and scalable techniques for modeling IR drop effects on timing.

November 14, 2024 01:30 pm

Scalable Modeling of Dynamic Voltage Compression on Timing

Tim Helvey

November 14, 2024 01:50 pm

Q&A: Scalable Modeling of Dynamic Voltage Compression on Timing

Q&A

November 14, 2024 02:00 pm

Indesign PG Fill Approach Using Pegasus & Innovus for Block Level IR Drop Minimization

Kok Loon Chin

November 14, 2024 02:20 pm

Q&A: Indesign PG Fill Approach Using Pegasus & Innovus for Block Level IR Drop Minimization

Q&A

November 14, 2024 02:30 pm

Implementation of Mesh Clocks on Iliad

Arun Hegde

November 14, 2024 02:50 pm

Q&A: Implementation of Mesh Clocks on Iliad

Q&A

November 14, 2024 03:00 pm

Enabling an Efficient SMVA-based Cross-Voltage Timing Corner Reduction and Signoff Methodology

Khusro Sajid

November 14, 2024 03:20 pm

Q&A: Enabling an Efficient SMVA-based Cross-Voltage Timing Corner Reduction and Signoff Methodology

Q&A

November 14, 2024 03:30 pm

PGV Model for Analog-on-Top IP

Ellen Liu

Prasanna Kumar Podavakam

Suryanarayan Prashant

November 14, 2024 03:50 pm

Q&A: PGV Model for Analog-on-Top IP

Q&A

November 14, 2024 04:00 pm

MCLKPLAN – Unified Clock Mesh Flow

Seth Merriman

November 14, 2024 04:20 pm

Q&A: MCLKPLAN – Unified Clock Mesh Flow

Q&A

November 14, 2024 04:30 pm

Timing Robustness Tempus-PI - A Way Forward for Analyzing Timing-Voltage Sensitive Paths

Shourya Shukla

November 14, 2024 04:50 pm

Q&A: Timing Robustness Tempus-PI - A Way Forward for Analyzing Timing-Voltage Sensitive Paths

Q&A

November 14, 2024 05:00 pm

High Symmetry and Reuse (HSR) Feedthrough Flow

Edward Larmore

Geoffrey Pilling

November 14, 2024 05:20 pm

Q&A: High Symmetry and Reuse (HSR) Feedthrough Flow

Q&A

November 14, 2024 01:20 pm

Track 6: SW or FW

The synergy between hardware and software is what sets us apart and drives our success.

Throughout this track, you’ll discover how our software and firmware teams are pushing boundaries, creating solutions that are robust, secure, and scalable. You’ll learn about the latest advancements, best practices, and innovative approaches in AI, Security and programming languages such as RUST.

November 14, 2024 01:30 pm

A System for Universal Computation on Encrypted Data (Cryptography)

Rohit Khera

Maciej Koprowski

November 14, 2024 01:50 pm

Q&A: A System for Universal Computation on Encrypted Data (Cryptography)

Q&A

November 14, 2024 02:00 pm

Simulator Packages to Shift Left Firmware Development

Venu B

Mahesh Potkar

November 14, 2024 02:20 pm

Q&A: Simulator Packages to Shift Left Firmware Development

Q&A

November 14, 2024 02:30 pm

AUTOSAR Compliant Security Architecture for Automotive Switches

Hari Krishna Elaprolu

November 14, 2024 02:50 pm

Q&A: AUTOSAR Compliant Security Architecture for Automotive Switches

Q&A

November 14, 2024 03:00 pm

Secure Storage for Embedded Devices

Dmytro Razinkov

November 14, 2024 03:20 pm

Q&A: Secure Storage for Embedded Devices

Q&A

November 14, 2024 03:30 pm

Harnessing AI Transforming Firmware Development

Sagar Feddewar

November 14, 2024 03:50 pm

Q&A: Harnessing AI Transforming Firmware Development

Q&A

November 14, 2024 04:00 pm

Secure Zero Touch Provisioning for Marvell Compute Devices

Rahul Sachdev

November 14, 2024 04:20 pm

Q&A: Secure Zero Touch Provisioning for Marvell Compute Devices

Q&A

November 14, 2024 04:30 pm

eBPF Based Dynamic Observability for Liquidsecurity HSM Firmware Applications

Neelakantam Gaddam

Gururaghavendra Chikkala

November 14, 2024 04:50 pm

Q&A: eBPF Based Dynamic Observability for Liquidsecurity HSM Firmware Applications

Q&A 

November 14, 2024 05:00 pm

AI-Driven Optimization of DSP Parameter Tuning with Neural Networks and Genetic Algorithms

Tingting Weng

November 14, 2024 05:20 pm

Q&A: AI-Driven Optimization of DSP Parameter Tuning with Neural Networks and Genetic Algorithms

Q&A

November 14, 2024 01:20 pm

Track 7: Post Silicon, Operations, and Engineering Compute or CAD Tools

These presentations and posters will focus on design automation (EDA), post-silicon validation and operations. Join us to get a view of how we are making the most of our tools to prepare for the future.   Learn about the design automation space, with a focus on the company’s M1DP design flow, the use of AI within the company to solve a variety of problems, and yield modeling, fuzzing techniques, and lessons learned from large hyper-scaler engagements.  

November 14, 2024 01:30 pm

A Deep Dive Into M1DP 3.0 Run Script Generation

Marc Galceran Oms

November 14, 2024 01:50 pm

Q&A: A Deep Dive Into M1DP 3.0 Run Script Generation

Q&A

November 14, 2024 02:00 pm

Enhancing Engineer Productivity and Debugging Efficiency with M1DP Copilot: A Retrieval-Augmented AI Model for M1DP Support

Jonas Casanova Bachs

November 14, 2024 02:20 pm

Q&A: Enhancing Engineer Productivity and Debugging Efficiency with M1DP Copilot: A Retrieval-Augmented AI Model for M1DP Support

Q&A

November 14, 2024 02:30 pm

Interop-GPT: A Generative AI Powered Platform for Streamlining Interoperability and Accelerating Data Center Deployment

Tingting Weng

November 14, 2024 02:50 pm

Q&A: Interop-GPT: A Generative AI Powered Platform for Streamlining Interoperability and Accelerating Data Center Deployment

Q&A

November 14, 2024 03:00 pm

Progress Report on GenAI Waveformer—Storage Waveform Modelling Using Generative AI

Ruwan Ratnayake

Han-Ting Chiang

Nitin Nangare

November 14, 2024 03:20 pm

Q&A: Progress Report on GenAI Waveformer—Storage Waveform Modelling Using Generative AI

Q&A

November 14, 2024 03:30 pm

Content Aware Yield Modelling

Greg Bazan

November 14, 2024 03:50 pm

Q&A: Content Aware Yield Modelling

Q&A

November 14, 2024 04:00 pm

Electrical Performance of TSMC 3nm N3P & N3E IP Testchips from Wafer Acceptance Testing Perspective

Siyuan Gu

November 14, 2024 04:20 pm

Q&A: Electrical Performance of TSMC 3nm N3P & N3E IP Testchips from Wafer Acceptance Testing Perspective

Q&A

November 14, 2024 04:30 pm

Incorporating Fuzzing to Enhance Product Quality

Ayuj Verma

Jijo Jose

Sai Venkata Manohar Venna

November 14, 2024 04:50 pm

Q&A: Incorporating Fuzzing to Enhance Product Quality

Q&A

November 14, 2024 05:00 pm

Lessons from the Future – Experiences in Hyperscalar Product Development

Paul Grzymkowski

Geordie Braceras

November 14, 2024 05:20 pm

Q&A: Lessons from the Future – Experiences in Hyperscalar Product Development

Q&A

November 14, 2024 01:20 pm

Track 8: Signal Integrity, Advanced Packaging, Process Technology, Board

The world of Advanced Packaging has many exciting technological advancements.  Presentations will focus on novel 2.5D and 3D package architectures and delve into electrical advancements in high-speed packaging.  Additionally, discover new thermal solutions essential for dissipating heat from high-power designs.

November 14, 2024 01:30 pm

TX FFE Coefficient Auto Tuning in C2M Scenarios

Tarun Kancharla

November 14, 2024 01:50 pm

Q&A: TX FFE Coefficient Auto Tuning in C2M Scenarios

Q&A

November 14, 2024 02:00 pm

Optimizing Core Material Selection for Semiconductor Packages

Tushar Chauhan

Shrinath Ramdas

November 14, 2024 02:20 pm

Q&A: Optimizing Core Material Selection for Semiconductor Packages

Q&A

November 14, 2024 02:30 pm

Novel Modular Stacked Package Architecture Evaluation Drives XSR Performance Beyond Original Design Standards

Aatreya Chakravarti

November 14, 2024 02:50 pm

Q&A: Novel Modular Stacked Package Architecture Evaluation Drives XSR Performance Beyond Original Design Standards

Q&A

November 14, 2024 03:00 am

Evaluation of Novel Liquid-Metal-Embedded-Elastomer for Thermal Interface Material Application

Assaad El Helou

November 14, 2024 03:20 pm

Q&A: Evaluation of Novel Liquid-Metal-Embedded-Elastomer for Thermal Interface Material Application

Q&A

November 14, 2024 03:30 pm

200G KGD (Known Good Die) ATE Testing Challenges

Ayad Azzawy

November 14, 2024 03:50 pm

Q&A: 200G KGD (Known Good Die) ATE Testing Challenges

Q&A

November 14, 2024 04:00 pm

Marvell 3D Sipho Engine- Behind the Scenes, Package Assembly Integration

Pushkraj Tumne

Hsiu-Che Wang

November 14, 2024 04:20 pm

Q&A: Marvell 3D Sipho Engine- Behind the Scenes, Package Assembly Integration

Q&A

November 14, 2024 04:30 pm

Optimization of SI/PI Package Performance for 2.5 D2D & 224G Applications

Meenakshi Upadhyaya

Srikrishna Sitaraman

Diane Peng

November 14, 2024 04:50 pm

Q&A: Optimization of SI/PI Package Performance for 2.5 D2D & 224G Applications

Q&A

November 14, 2024 05:00 pm

3D Next Generation Test Vehicle / Thermal Challenges

Kazin Blacklow

November 14, 2024 05:20 pm

Q&A: 3D Next Generation Test Vehicle / Thermal Challenges

Q&A

November 14, 2024 01:20 pm

Track 9: Marvell Fundamental Technology/Product Overview

These presentations will provide everyone at Marvell with a clear and concise understanding of the technologies and strategic initiatives driving our success. This is a great opportunity to grasp the end-to-end lifecycle of a Marvell product. 

On Day 3, learn about Marvell’s product lines, their key advantages, how they are used and by what customers. Hear a discussion on key financial terms, Marvell’s approach to sustainability, some of our key value-add IP, and perspectives on the Marvell OS. 

November 14, 2024 01:30 pm

Connectivity (Electrical and Optical)

Venu Balasubramonian

November 14, 2024 01:50 pm

Q&A: Connectivity (Electrical and Optical)

Q&A

November 14, 2024 02:00 pm

Switch

Itay Peled

November 14, 2024 02:20 pm

Q&A: Switch

November 14, 2024 02:30 pm

SerDes IP

Mike Sorna

November 14, 2024 02:50 pm

Q&A: SerDes IP

Q&A

November 14, 2024 03:00 pm

ESG/Sustainability

Alua Suleimenova

November 14, 2024 03:20 pm

Q&A: ESG/Sustainability

Q&A

November 14, 2024 03:30 pm

Marvell OS

Bill Reaves

November 14, 2024 03:50 pm

Q&A: Marvell OS

November 14, 2024 04:00 pm

Financial 101

Avi Roy

November 14, 2024 04:20 pm

Q&A: Financial 101